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? semiconductor components industries, llc, 2016 april, 2016 ? rev. 3 1 publication order number: ncp81071/d ncp81071 dual 5 a high speed low-side mosfet drivers with enable ncp81071 is a high speed dual low?side mosfets driver. it is capable of providing large peak currents into capacitive loads. this driver can deliver 5 a peak current at the miller plateau region to help reduce the miller effect during mosfets switching transition. this driver also provides enable functions to give users better control capability in different applications. ena and enb are implemented on pin 1 and pin 8 which were previously unused in the industry standard pin?out. they are internally pulled up to driver?s input voltage for active high logic and can be left open for standard operations. this part is available in msop8?ep package , soic8 package and wdfn8 3 mm x 3 mm package . features ? high current drive capability 5 a ? ttl/cmos compatible inputs independent of supply voltage ? industry standard pin?out ? high reverse current capability (6 a) peak ? enable functions for each driver ? 8 ns typical rise and 8 ns typical fall times with 1.8 nf load ? typical propagation delay times of 20 ns with input falling and 2 0 ns with input rising ? input voltage from 4.5 v to 20 v ? dual outputs can be paralleled for higher drive current ? these devices are pb?free, halogen free/bfr free and are rohs compliant applications ? server power ? telecommunication, datacenter power ? synchronous rectifier ? switch mode power supply ? dc/dc converter ? power factor correction ? motor drive ? renewable energy, solar inverter see detailed ordering and shipping information in the packag e dimensions section on page 11 of this data sheet. ordering information marking diagrams www. onsemi.com soic?8 d suffix case 751 xxxx alyw 1 8 pin connections ina ena 1 8 (top view) xx = specific device code a = assembly location l = wafer lot y = year w = work week m = date code = pb?free package (note: microdot may be in either location) outb vdd outa enb inb gnd msop?8 z suffix case 846am wdfn8 mn suffix case 511cd xxxx ayw xx m 1 1
ncp81071 www. onsemi.com 2 vdd vdd vdd vdd ref ref ref ref logic a channel logic b channel uvlo vdd vdd vdd vdd ina ena gnd inb enb outa outb vdd figure 1. ncp81071 block diagram ncp81071a ncp81071b ncp81071c vdd vdd ref ref ref ref logic a channel logic b channel uvlo vdd vdd vdd vdd ina ena gnd inb enb outa outb vdd vdd vdd vdd ref ref ref ref logic a channel logic b channel uvlo vdd vdd vdd vdd ina ena gnd inb enb outa outb vdd table 1. pin description pin no. symbol description 1 ena enable input for the driver channel a with logic compatible threshold and hysteresis. this pin is used to en- able and disable the driver output. it is internally pulled up to vdd with a 200 k resistor for active high op- eration. the output of the pin when the device is disabled will be always low. 2 ina input of driver channel a which has logic compatible threshold and hysteresis. if not used, this pin should be connected to either vdd or gnd. it should not be left unconnected. 3 gnd common ground. this ground should be connected very closely to the source of the power mosfet. 4 inb input of driver channel b which has logic compatible threshold and hysteresis. if not used, this pin should be connected to either vdd or gnd. it should not be left unconnected. 5 outb output of driver channel b. the driver is able to provide 5 a drive current to the gate of the power mosfet. 6 vdd supply voltage. use this pin to connect the input power for the driver device. 7 outa output of driver channel a. the driver is able to provide 5 a drive current to the gate of the power mosfet. 8 enb enable input for the driver channel b with logic compatible threshold and hysteresis. this pin is used to en- able and disable the driver output. it is internally pulled up to vdd with a 200 k resistor for active high op- eration. the output of the pin when the device is disabled will be always low.
ncp81071 www. onsemi.com 3 typical application circuit 1 2 3 4 8 7 6 5 ina ena gnd inb enb outa outb vdd ncp81071 table 2. absolute maximum ratings value unit min max supply voltage vdd ?0.3 24 v output current (dc) iout_dc 0.3 a reverse current (pulse< 1 s) 6.0 a output current (pulse < 0.5 s) iout_pulse 6.0 a input voltage ina, inb ?6.0 vdd+0.3 v enable voltage ena, enb ?0.3 vdd+0.3 output voltage outa, outb ?0.3 vdd+0.3 v output voltage (pulse < 0.5 s) outa, outb ?3.0 vdd+3.0 v junction operation temperature t j ?40 150 c storage temperature t stg ?65 160 electrostatic discharge human body model, hbm 4000 v charge device model, cdm 1000 outa outb latch?up protection 500 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. table 3. recommended operating conditions parameter rating unit vdd supply voltage 4.5 to 20 v ina, inb input voltage ?5.0 to vdd v ena, enb input voltage 0 to vdd v junction temperature range ?40 to +140 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. table 4. thermal information package ja ( c/w) jc ( c/w) soic?8 115 50 msop?8 ep 39 4.7 wdfn8 3x3 39 4.7
ncp81071 www. onsemi.com 4 table 5. input/output table ena enb ina inb ncp81071a ncp81071b ncp81071c outa outb outa outb outa outb h h l l h h l l h l h h l h h l l h h h h h h l l h h l l l h h h h l l h h l h l l any any l l l l l l any any x (note 1) x (note 1) l l l l l l x (note 1) x (note 1) l l h h l l h l x (note 1) x (note 1) l h h l l h h h x (note 1) x (note 1) h l l h h l l l x (note 1) x (note 1) h h l l h h l h 1. floating condition, internal resistive pull up or pull down configures output condition product matrix ncp81071a ncp81071b ncp81071c
ncp81071 www. onsemi.com 5 table 6. electrical characteristics (typical values: v dd =12 v, 1 f from v dd to gnd, t a = t j = ?40 c to 140 c, typical at t amb = 25 c, unless otherwise specified) parameter symbol test conditions min typ max units supply voltage vdd under voltage lockout (rising) v ccr vdd rising 3.5 4.0 4.5 v vdd under voltage lockout (hysteresis) v cch 400 mv operating current (no switching) i dd ina = 0, inb = 5 v, ena = enb = 0 ina = 5 v, inb = 0, ena = enb = 0 ina = 0, inb = 5 v, ena = enb = 5 v ina = 5 v, inb = 0, ena = enb = 5 v 1.4 3 ma vdd under voltage lockout to output delay (note 2) vdd rising 10 s inputs high threshold v thh input rising from logic low 1.8 2.0 2.2 v low threshold v thl input falling from logic high 0.8 1.0 1.2 v ina, inb pull?up resistance outa = outb = inverter configuration 200 k ina, inb pull?down resistance outa = outb = buffer configuration 200 k outputs output resistance high r oh iout = ?10 ma 0.8 2 output resistance low r ol iout = +10 ma 0.8 2 peak source current (note 3) i source outa/outb = gnd 200 ns pulse 5 a miller plateau source current (note 3) i source outa/outb = 5.0 v 200 ns pulse 4.5 a peak sink current (note 3) i sink outa/outb = vdd 200 ns pulse 5 a miller plateau sink current (note 3) i sink outa/outb = 5.0 v 200 ns pulse 3.5 a enable high?level input voltage v in_h low to high transition 1.8 2.0 2.2 v low?level input voltage v in_l high to low transition 0.8 1.0 1.2 v ena, enb pull?up resistance 200 k propagation delay time (en to out) (notes 2, 4) t d3 c load = 1.8 nf 16 20 29 ns propagation delay time (en to out) (notes 2, 4) t d4 c load = 1.8 nf 16 20 29 ns switching characteristics propagation delay time low to high, in rising (in to out) (notes 2, 4) t d1 c load = 1.8 nf 16 20 29 ns propagation delay time high to low, in falling (in to out) (notes 2, 4) t d2 c load = 1.8 nf 16 20 29 ns rise time (note 4) t r c load = 1.8 nf 8 15 ns fall time (note 4) t f c load = 1.8 nf 8 15 ns delay matching between 2 channels (note 5) t m ina = inb, outa and outb at 50% transition point 1 4 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. guaranteed by design. 3. not production tested, guaranteed by design and statistical analysis. 4. see timing diagrams in figure 2, figure 3, figure 4 and figure 5. 5. guaranteed by characterization.
ncp81071 www. onsemi.com 6 t d3 t d4 input enable output 2 v 2 v 1 v 1 v 90% 10% t d3 t d4 input enable output 2 v 2 v 1 v 1 v 90% 10% figure 2. enable function for non?inverting input driver operation figure 3. enable function for inverting input driver operation t d1 t d2 input enable output 2 v 2 v 1 v 1 v 90% 10% t r t f t d1 t d2 input enable output 2 v 2 v 1 v 1 v 90% 10% figure 4. non?inverting input driver operation figure 5. inverting input driver operation
ncp81071 www. onsemi.com 7 typical characteristics figure 6. supply current vs. switching frequency (v dd = 4.5 v) figure 7. supply current vs. switching frequency (v dd = 8 v) frequency (khz) frequency (khz) 2000 1400 1200 1000 800 400 200 0 0 10 30 40 60 70 90 100 1250 1000 750 2000 500 250 0 0 20 40 80 100 120 140 180 figure 8. supply current vs. switching frequency (v dd = 12 v) figure 9. supply current vs. switching frequency (v dd = 15 v) frequency (khz) frequency (khz) figure 10. supply current vs. switching frequency (v dd = 18 v) figure 11. supply current vs. supply voltage (c load = 2.2 nf) frequency (khz) supply voltage (v) 18 16 14 12 10 8 6 4 0 20 40 60 80 100 120 supply current (ma) supply current (ma) supply current (ma) supply current (ma) supply current (ma) supply current (ma) 600 1600 1800 20 50 80 v dd = 4.5 v 470 pf 1 nf 2.2 nf 4.7 nf 10 nf v dd = 8.0 v 470 pf 1 nf 2.2 nf 4.7 nf 10 nf 1500 1750 60 160 1250 1000 750 2000 500 250 0 0 30 60 120 150 180 210 270 v dd = 12 v 470 pf 1 nf 2.2 nf 4.7 nf 10 nf 1500 1750 90 240 1250 1000 750 2000 500 250 0 0 30 60 120 150 180 210 270 v dd = 15 v 470 pf 1 nf 2.2 nf 4.7 nf 10 nf 1500 1750 90 240 1250 1000 750 2000 500 250 0 0 30 60 120 150 180 210 270 v dd = 18 v 470 pf 1 nf 2.2 nf 4.7 nf 10 nf 1500 1750 90 240 20 c load = 2.2 nf 50 khz 2 mhz 1 mhz 500 khz 200 khz 100 khz
ncp81071 www. onsemi.com 8 typical characteristics figure 12. supply current vs. supply voltage (c load = 4.7 nf) figure 13. supply current vs. supply voltage (ncp81071a) supply voltage (v) supply voltage (v) 18 16 14 12 10 8 6 4 0 20 40 60 80 120 140 160 18 16 14 12 10 8 6 4 0 0.2 0.4 0.8 1.0 1.4 1.8 2.0 figure 14. supply current vs. supply voltage (ncp81071b) figure 15. supply current vs. supply voltage (ncp81071c) figure 16. rise time vs. temperature figure 17. fall time vs. temperature temperature ( c) 120 100 80 60 20 0 ?20 ?40 0 2 4 6 8 10 12 supply current (ma) supply current (ma) t r , rise time (ns) 20 100 c load = 4.7 nf 50 khz 2 mhz 1 mhz 500 khz 200 khz 100 khz 20 0.6 1.2 1.6 input = gnd input = v dd supply voltage (v) 18 16 14 12 10 8 6 4 0 0.2 0.4 0.8 1.0 1.4 1.8 2.0 supply current (ma) 20 0.6 1.2 1.6 input = gnd input = v dd supply voltage (v) 18 16 14 12 10 8 6 4 0 0.2 0.4 0.8 1.0 1.4 1.8 2.0 supply current (ma) 20 0.6 1.2 1.6 input = gnd input = v dd 40 140 v dd = 20 v v dd = 15 v v dd = 10 v v dd = 5 v temperature ( c) 120 100 80 60 20 0 ?20 ?40 0 2 4 6 8 10 12 t f , fall time (ns) 40 140 v dd = 20 v v dd = 15 v v dd = 10 v v dd = 5 v
ncp81071 www. onsemi.com 9 typical characteristics figure 18. propagation delay t d1 vs. supply voltage figure 19. propagation delay t d2 vs. supply voltage v dd , supply voltage (v) v dd , supply voltage (v) 18 16 14 12 10 8 6 4 0 5 10 15 20 25 30 18 16 14 12 10 8 6 4 0 5 10 15 20 25 30 figure 20. fall time t f vs. supply voltage figure 21. rise time t r vs. supply voltage v dd , supply voltage (v) v dd , supply voltage (v) 18 16 14 12 10 8 6 4 0 5 10 15 20 25 30 18 16 14 12 10 8 6 4 0 5 10 15 20 25 30 figure 22. output behavior vs. supply voltage ncp81071a (inverting) 10 nf between output and gnd, ina = gnd, ena = vdd figure 23. output behavior vs. supply voltage ncp81071a (inverting) 10 nf between output and gnd, ina = gnd, ena = vdd t d1 , delay time (ns) t d2 , delay time (ns) t f , fall time (ns) t r , rise time (ns) output vdd output vdd 20 20 35 470 pf 1.0 nf 2.2 nf 4.7 nf 10 nf 20 470 pf 1.0 nf 2.2 nf 4.7 nf 10 nf 20 10 nf 4.7 nf 2.2 nf 1.0 nf 470 pf 10 nf 4.7 nf 2.2 nf 1.0 nf 470 pf
ncp81071 www. onsemi.com 10 typical characteristics figure 24. output behavior vs. supply voltage ncp81071a (inverting) 10 nf between output and gnd, ina = vdd, ena = vdd figure 25. output behavior vs. supply voltage ncp81071a (inverting) 10 nf between output and gnd, ina = vdd, ena = vdd figure 26. output behavior vs. supply voltage ncp81071b (non?inverting) 10 nf between output and gnd, ina = vdd, ena = vdd figure 27. output behavior vs. supply voltage ncp81071b (non?inverting) 10 nf between output and gnd, ina = vdd, ena = vdd figure 28. output behavior vs. supply voltage ncp81071b (non?inverting) 10 nf between output and gnd, ina = gnd, ena = vdd figure 29. output behavior vs. supply voltage ncp81071b (non?inverting) 10 nf between output and gnd, ina = gnd, ena = vdd output vdd output vdd output vdd output vdd output vdd output vdd
ncp81071 www. onsemi.com 11 layout guidelines the switching performance of ncp81071 highly depends on the design of pcb board. the following layout design guidelines are recommended when designing boards using these high speed drivers. place the driver as close as possible to the driven mosfet. place the bypass capacitor between vdd and gnd as close as possible to the driver to improve the noise filtering. it is preferred to use low inductance components such as chip capacitor and chip resistor. if vias are used, connect several paralleled vias to reduce the inductance of the vias. minimize the turn-on/sourcing current and turn-off/sinking current paths in order to minimize stray inductance. otherwise high di/dt established in these loops with stray inductance can induce significant voltage spikes on the output of the driver and mosfet gate terminal. keep power loops as short as possible by paralleling the source and return traces (flux cancellation). keep low level signal lines away from high level power lines with a lot of switching noise. place a ground plane for better noise shielding. beside noise shielding, ground plane is also useful for heat dissipation. ncp81071 dfn and msop package have thermal pad for: 1) quiet gnd for all the driver circuits; 2) heat sink for the driver. this pad must be connected to a ground plane and no switching currents from the driven mosfet should pass through the ground plane under the driver. to maximize the heatsinking capability, it is recommended several ground layers are added to connect to the ground plane and thermal pad. a via array within the area of package can conduct the heat from the package to the ground layers and the whole pcb board. the number of vias and the size of ground plane are determined by the power dissipation of ncp81071 (vdd voltage, switching frequency and load condition), the air flow condition and its maximum junction temperature. ordering information part number output configuration temperature range ( c) package type shipping ? ncp81071adr2g dual inverting ?40 to +140 soic?8 (pb?free) 2500 / tape & reel ncp81071bdr2g dual non inverting ncp81071cdr2g one inverting one non inverting ncp81071azr2g dual inverting msop8 ep (pb?free) 3000 / tape & reel ncp81071bzr2g dual non inverting ncp81071czr2g one inverting one non inverting NCP81071AMNTXG dual inverting wdfn8 (pb?free) 3000 / tape & reel ncp81071bmntxg dual non inverting ncp81071cmntxg one inverting one non inverting ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp81071 www. onsemi.com 12 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp81071 www. onsemi.com 13 package dimensions msop8 ep, 3x3 case 846am issue o notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm in excess of maximum material condition. 4. dimension d does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. dimension e does not include inter- lead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 mm per side. dimensions d and e are determined at datum f. 5. datums a and b to be determined at datum f. 6. a1 is defined as the vertical distance from the seating plane to the lowest point on the package body. dim min max millimeters a ??? 1.10 a1 0.05 0.15 b 0.25 0.40 c 0.13 0.23 d 2.90 3.10 d2 1.78 ref e2 1.42 ref e 0.65 bsc l 0.40 0.70 l2 0.254 bsc e 4.75 5.05 e1 2.90 3.10 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* recommended a m 0.08 b c s s f c 0.10 c detail a 8x 0.85 5.35 0.65 pitch 8x 0.42 dimensions: millimeters
ncp81071 www. onsemi.com 14 package dimensions wdfn8 3x3, 0.65p case 511cd issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. ???? ???? ???? a d e b c 0.10 pin one 2x reference 2x top view side view bottom view l d2 e2 c c 0.10 c 0.05 c 0.05 a1 seating plane 8x note 3 b 8x 0.10 c 0.05 c a b b dim min max millimeters a 0.70 0.80 a1 0.00 0.05 b 0.25 0.35 d 3.00 bsc d2 2.05 2.25 e 3.00 bsc e2 1.10 1.30 e 0.65 bsc l 0.30 0.50 1 4 8 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.65 pitch 1.36 3.30 1 dimensions: millimeters 0.63 8x note 4 0.40 8x detail a a3 0.20 ref a3 a detail b l1 detail a l alternate constructions ??? ??? ??? 0.00 0.15 outline package e recommended k 5 2.31 e/2 k 0.20 ??? on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp81071/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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